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HY62SF16806B Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM
Revision History
Revision No 00 01 History Initial Release Draft Date May.29.2001 Remark Preliminary Final
DC Electrical Characteristics Oct.22.2002 - ICC changed 4mA -> 3mA - ICC1 changed 25mA at 70ns -> 15mA at 70ns - ICC1 changed 3mA at 1us -> 2mA at 1us - ISB (TTL) changed 50uA -> 300uA AC Test Loads - (R1//R2) 4091Ohm // 3273Ohm -> 3070Ohm // 3150Ohm AC Test Conditions - Output Load changed 5pF -> 30pF - Input Pulse Level 0.4V to 1.6V -> 0.2V to Vcc-0.2 Data Retention Electric Characteristic - ICCDR LL-Part changed 20uA -> 10uA
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.01 /Oct. 2002 Hynix Semiconductor
HY62SF16806B
DESCRIPTION
The HY62SF16806B is a high speed, super low power and 8Mbit full CMOS SRAM organized as 524,288 words by 16bits. The HY62SF16806B uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly wellsuited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
* Fully static operation and Tri-state output * TTL compatible inputs and outputs * Battery backup(LL/SL-part) - 1.2V(min) data retention * Standard pin configuration - 48-FBGA
FEATURES
Product Voltage Speed No. (V) (ns) HY62SF16806B-C 1.65~2.3 70/85/100 HY62SF16806B-I 1.65~2.3 70/85/100 Note 1. C : Commercial, I : Industrial 2. Current value is max. Operation Current/Icc(mA) 3 3 Standby Current(uA) LL SL 15 8 15 8 Temperature (C) 0~70 -40~85
PIN CONNECTION ( Top View )
1 2 /OE /UB 3 A0 A3 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 /CS1 IO2 IO4 IO5 IO6 6 CS2 IO1
ADD INPUT BUFFER
BLOCK DIAGRAM
ROW DECODER SENSE AMP
A B C D E F G H
/LB IO9
I/O1
COLUMN DECODER
I/O8 DATA I/O BUFFER
PRE DECODER
IO10 IO11 A5 Vss Vcc IO12 A17 IO13 Vss
IO3 Vcc Vss IO7
A18
MEMORY ARRAY 512K x 16
WRITE DRIVER
I/O9
BLOCK DECODER
IO15 IO14 A14 IO16 NC A1 A8 A12 A9
I/O16
/WE IO8 A11 NC
/CS1 CS2 /OE /LB /UB /WE
PIN DESCRIPTION
Pin Name /CS1, CS2 /WE /OE /LB /UB Pin Function Chip Select Write Enable Output Enable Lower Byte Control(I/O1~I/O8) Upper Byte Control(I/O9~I/O16) Pin Name I/O1~I/O16 A0~A18 Vcc Vss NC Pin Function Data Inputs / Outputs Address Inputs Power(1.65V~2.3V) Ground No Connection
Rev.01 /Oct. 2002
2
HY62SF16806B
ORDERING INFORMATION
Part No. Speed HY62SF16806B-DFC 70/85/100 HY62SF16806B-SFC 70/85/100 HY62SF16806B-DFI 70/85/100 HY62SF16806B-SFI 70/85/100 Note 1. C : Commercial, I : Industrial Power LL-part SL-part LL-part SL-part Package FBGA FBGA FBGA FBGA Temp. C C I I
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VIN, VOUT Vcc TA TSTG PD TSOLDER Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.3 to Vcc+0.3 -0.3 to 2.6 0 to 70 -40 to 85 -55 to 150 1.0 260 * 10 Unit V V C C C W C * sec Remark
HY62SF16806B-C HY62SF16806B-I
Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1 H X X L L L CS2 X L X H H H /WE X X X H H H /OE X X X H H L /LB X X H L X L H L L H L /UB X X H X L H L L H L L
Mode
Deselected Output Disabled Read
L
H
L
X
Write
I/O Pin I/O1~I/O8 I/O9~I/O16 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z DOUT DOUT DOUT DIN Hi-Z Hi-Z DIN DIN DIN
Power Standby Active Active
Active
Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. UB, LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8. When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.01 /Oct. 2002
2
HY62SF16806B
RECOMMENDED DC OPERATING CONDITION
Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 1.65 0 1.4 -0.3(1) Typ. 1.8 0 Max. 2.3 0 Vcc+0.3 0.4 Unit V V V V
Note : 1. VIL = -1.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
Vcc = 1.65V~2.3V, TA = 0C to 70C / -40C to 85C Sym Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc Vss < VOUT < Vcc, /CS1 = VIH or CS2=VIL or ILO Output Leakage Current /OE = VIH or /WE = VIL or /UB = VIH , /LB = VIH /CS1 = VIL, CS2=VIH, Icc Operating Power Supply Current VIN = VIH or VIL, II/O = 0mA /CS1 = VIL, CS2 = VIH, VIN = VIH or VIL, Cycle Time = Min, 100% Duty, II/O = 0mA ICC1 Average Operating Current /CS1 < 0.2V, CS2 > Vcc-0.2V, VIN < 0.2V or VIN > Vcc-0.2V, Cycle Time = 1us, 100% Duty, II/O = 0mA /CS1 = VIH or CS2 = VIL or /UB, /LB = VIH ISB Standby Current (TTL Input) VIN = VIH or VIL /CS1 > Vcc - 0.2V or SL CS2 < Vss + 0.2V or ISB1 Standby Current (CMOS Input) /UB, /LB > Vcc - 0.2V LL VIN > Vcc - 0.2V or VIN < Vss + 0.2V VOL Output Low IOL = 0.1mA VOH Output High IOH = -0.1mA Note : 1. Typical values are at Vcc = 1.8V, TA = 25C 2. Typical values are sampled and not 100% tested Min -1 -1 Typ1. Max 1 1 Unit uA uA
3 15 2
mA mA mA
300 1 1.4 8 15 0.2 -
uA uA uA V V
CAPACITANCE
(Temp = 25C, f = 1.0MHz) Symbol Parameter CIN Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE) COUT Output Capacitance (I/O) Note : These parameters are sampled and not 100% tested Condition VIN = 0V VI/O = 0V Max. 8 10 Unit PF PF
Rev.01 /Oct. 2002
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HY62SF16806B
AC CHARATERISTICS
Vcc = 1.65V~2.3V, TA = 0C to 70C / -40C to 85C # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol Parameter Min. 70 10 5 10 0 0 0 10 70 60 60 60 0 50 0 0 30 0 5 -70 Max. 70 70 35 70 20 20 20 20 Min. 85 10 5 10 0 0 0 10 85 70 70 70 0 60 0 0 35 0 5 -85 Max. 85 85 40 85 30 30 30 25 Min 100 10 5 10 0 0 0 15 100 80 80 80 0 70 0 0 45 0 10 -10 Max. 100 100 45 100 30 30 30 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
READ CYCLE TRC Read Cycle Time TAA Address Access Time TACS Chip Select Access Time TOE Output Enable to Output Valid TBA /LB, /UB Access Time TCLZ Chip Select to Output in Low Z TOLZ Output Enable to Output in Low Z TBLZ /LB, /UB Enable to Output in Low Z TCHZ Chip Deselection to Output in High Z tOHZ Out Disable to Output in High Z TBHZ /LB, /UB Disable to Output in High Z TOH Output Hold from Address Change WRITE CYCLE TWC Write Cycle Time TCW Chip Selection to End of Write TAW Address Valid to End of Write TBW /LB, /UB Valid to End of Write TAS Address Set-up Time TWP Write Pulse Width tWR Write Recovery Time tWHZ Write to Output in High Z tDW Data to Write Time Overlap tDH Data Hold from Write Time tOW Output Active from End of Write
AC TEST CONDITIONS
TA = 0C to 70C / -40C to 85C, unless otherwise specified PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW Output Load Other Value 0.2V to Vcc-0.2V 5ns 0.9V CL = 30pF + 1TTL Load CL = 30pF + 1TTL Load
AC TEST LOADS
VT M = 1.8V
3070 O hm D
OUT
CL(1)
3150 O hm
Note 1. Including jig and scope capacitance
Rev.01 /Oct. 2002
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HY62SF16806B
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC ADDR tAA /CS1 tACS tOH
CS2 tCHZ(3) tBA /UB ,/ LB tBHZ(3) /OE tOLZ(3) tBLZ(3) Data Valid tOE tOHZ(3)
Data Out
High-Z
tCLZ(3)
READ CYCLE 2(Note 1,2,4)
tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH
READ CYCLE 3(Note 1,2,4)
/CS1 /UB, /LB
CS2 tACS tCLZ(3) Data Out Data Valid tCHZ(3)
Notes: 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status. 2. /OE = VIL 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
Rev.01 /Oct. 2002
5
HY62SF16806B
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC ADDR tCW /CS1 tWR(2)
CS2
tAW tBW
/UB,/LB tWP /WE tAS Data In High-Z tWHZ(3,7) Data Out tDW Data Valid tOW (5) (6) tDH
WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled)
tWC ADDR tAS /CS1 tAW CS2 tBW /UB,/LB tWP /WE tDW Data In High-Z Data Valid tDH tCW tWR(2)
Data Out
High-Z
Rev.01 /Oct. 2002
6
HY62SF16806B
Notes: 1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and a Low /UB and/or /LB. 2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0C to 70C / -40C to 85C Symbol Parameter VDR Vcc for Data Retention Test Condition /CS1 > Vcc - 0.2V or CS2 < Vss + 0.2V or /UB, /LB > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V, /CS1 > Vcc - 0.2V or CS2 < Vss + 0.2V or /UB, /LB > Vcc - 0.2V VIN > Vcc - 0.2V or VIN < Vss + 0.2V Min 1.2 Typ1. Max 2.3 Unit V
SL
-
-
8
uA
Iccdr
Data Retention Current
LL
0
1 -
12 -
uA ns ns
tCDR tR
Chip Deselect to Data Retention Time Operating Recovery Time
See Data Retention Timing Diagram tRC
Notes: 1. Typical values are under the condition of TA = 25C . 2. tRC is read cycle time.
Rev.01 /Oct. 2002
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HY62SF16806B
DATA RETENTION TIMING DIAGRAM 1
VCC 1.65V tCDR DATA RETENTION MODE tR
VIH VDR CS1>VCC-0.2V /CS1 VSS
DATA RETENTION TIMING DIAGRAM 2
VCC 1.65V tCDR CS2 VDR DATA RETENTION MODE tR
0.4V VSS CS2<0.2V
Rev.01 /Oct. 2002
8
HY62SF16806B
PACKAGE INFORMATION
48ball Fine Pitch Ball Grid Array Package (F)
BOTTOM VIEW
B A A1 CORNER INDEX AREA 6 A B C C D E F G H C1/2 C1 A 5 4 3 2 1
TOP VIEW
B1/2
B1
SIDE VIEW
5
C
E1 E2 E SEATING PLANE A 4
r
3 D(DIAMETER)
Symbol A B B1 C C1 D E E1 E2 r
Min. 5.9 8.4 0.3 0.9 0.20 -
Typ. 0.75 3.75 6.0 5.25 8.5 0.35 1.0 0.76 0.25 -
Max. 6.1 8.6 0.4 1.10 0.30 0.08
Note 1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION "D" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION.
Rev.01 /Oct. 2002
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HY62SF16806B
MARKING INSTRUCTION
Package
H Y
Marking Example
S F 6 8 0 6 B
fBGA
c
s
s
t
y
w
w
p
x
x
x
x
x
K
O
R
Index
* HYSF6806B *c : Part Name : Power Consumption -D -S : Speed - 70 - 85 - 10 *t : Temperature -C -I : 70ns : 85ns : 100ns : Commercial ( 0 ~ 70 C) ) : Industrial ( -40 ~ 85 C ) : Low Low Power : Super Low Power
* ss
*y * ww *p * xxxxx * KOR Note - Capital Letter - Small Letter
: Year (ex : 0 = year 2000, 1= year 2001) : Work Week ( ex : 12 = work week 12 ) : Process Code : Lot No. : Origin Country : Fixed Item : Non-fixed Item
Rev.01 /Oct. 2002
10

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